The invention relates to a method and apparatus for addressing multi-bank memory and in particular relates to system for enabling a memory controller configured for use with N banks of memory to address M banks of memory. Dynamic Random Access Memory (DRAM) technology is continually evolving. Recently, DRAM evolved to a standard known as Synchronous DRAM (SDRAM). This version differs from previous DRAM technologies in that control and data signals are synchronized with a clock. Existing DRAMs, such as Fast Page Mode (FPM) and Extended Data Out (EDO), contain a single range of addresses, while SDRAM typically contain multiple ranges of addresses referred to as banks. These multiple ranges of address allow for more complex accesses to the DRAM. For example, address location 1 would only occur one time in a FPM/EDO DRAM while it would occur twice in a two bank DRAM (Bank A address location 1 and Bank B address location 1). As SDRAMs continued to evolve, they will increase in the number of banks. 16 Mb SDRAMs typically contain two banks. Newer 64 Mb SDRAMs typically contain four banks. Future SDRAMs will likely contain 8 or 16 banks.
The concept of banks can create a problem of compatibility between different versions and generations of SDRAM. Memory controllers designed to operate with a specific number of banks will not be able to operate with the increased number of banks associated with newer SDRAM generations. This may prohibit systems based on a particular memory controller to take advantage of densities and prices of newer SDRAM generations and may even limit the system's lifetime due to limited availability of older SDRAM generations.